Engineering knowledge for production EDA.

Practical guides, scripting tutorials, and engineering best practices from the SkyCadEda team — covering EDA automation, Cadence SKILL, PDK enablement, physical verification, and layout automation.

113 notes · 8 topics · latest

Latest notes

  1. Antenna Checks in Physical VerificationAntenna checks protect gate oxide from plasma-induced charging. How antenna ratios, diode fixes, jumper reroutes, debug, and signoff evidence fit together.
  2. Design Data Management in Custom IC FlowsDesign data management for custom IC flows: library and cellview versioning, workspace discipline, release snapshots, and automation for reproducible signoff.
  3. Hierarchical SoC Floorplanning StrategiesMaster the art of hierarchical floorplanning to optimize area, timing, and routability in large-scale System-on-Chip (SoC) designs for advanced nodes.
  4. Mixed-Signal Verification ArchitecturesExplore the design of robust mixed-signal verification environments, focusing on co-simulation efficiency, behavioral modeling, and regression strategies.
  5. Scalable CAD Tooling for Modern SoC DesignBuild robust, tool-agnostic CAD infrastructure for large-scale SoC projects by leveraging modular wrappers, resource scheduling, and reproducibility.

Physical verification22 notes

  1. Antenna Checks in Physical VerificationAntenna checks protect gate oxide from plasma-induced charging. How antenna ratios, diode fixes, jumper reroutes, debug, and signoff evidence fit together.
  2. Advanced DRC and Signoff StrategiesMaster the transition from simple rule checking to complex signoff strategies, ensuring layout reliability across nanometer nodes and PDK constraints.
  3. Metal Fill and Density Signoff DisciplineHow density windows, fill insertion, and post-fill verification fit together, and the habits that keep density signoff clean through tapeout.
  4. Debugging LVS Shorts and OpensA practical workflow for debugging LVS shorts and opens, from reading discrepancy reports to isolating layout causes and closing clean.
  5. Anatomy of a Design Rule Check DeckHow design rule check decks are organized, which rule families they encode, and how teams run and debug them through physical verification signoff.
  6. EM and IR Checks in Physical VerificationLearn how electromigration and IR drop checks fit into physical verification, from current maps and limits to signoff-ready power grid closure.
  7. Layout Versus Schematic DisciplineHow teams make layout versus schematic checks pass reliably: netlist extraction, device matching, clean-by-design habits, and disciplined LVS debugging.
  8. DRC Baseline and Waiver DisciplineDesign rule checking works best as a baseline discipline: clean trees, categorized violations, documented waivers, and automated regression runs before tapeout.
  9. Physical Verification Handoff DisciplineA practical, reproducible physical verification workflow for teams that want predictable DRC and LVS closure with clear ownership and release-ready evidence.
  10. DRC and LVS Closure EvidenceLearn how to assemble clear DRC and LVS closure evidence, separate rule violations from connectivity mismatches, and support ASIC signoff reviews.
  11. DRC and LVS Flow SequencingLearn how to sequence DRC and LVS checks through an ASIC implementation flow so teams find physical and connectivity defects at the right stage.
  12. DRC and LVS Waiver GovernanceBuild a controlled DRC and LVS waiver process with clear ownership, reproducible evidence, expiration rules, and release-level review gates.
  13. DRC vs LVS Signoff CheckpointsLearn where DRC and LVS checks fit in ASIC flows, what each checkpoint proves, and how teams coordinate inputs, results, and signoff evidence.
  14. DRC and LVS Debug HandoffUnderstand how DRC and LVS failures differ, how evidence should move between teams, and how to build a traceable physical-verification handoff.
  15. PVS Physical VerificationLearn how Cadence PVS physical verification automates DRC, LVS, ERC, and reliability checks for custom IC tapeout readiness.
  16. Calibre PERC Reliability GuideLearn how Calibre PERC automates reliability verification for ESD, latch-up, power intent, and custom IC signoff across advanced nodes.
  17. Synopsys IC Validator GuideLearn Synopsys IC Validator automation for DRC, LVS, pattern matching, rule QA, debug, and scalable physical verification signoff.
  18. Cadence Assura DRC LVS GuideLearn Cadence Assura DRC and LVS setup, rule deck automation, waiver control, and migration planning for custom IC verification flows.
  19. Cadence Pegasus VerificationCadence Pegasus verification guide covering DRC, LVS, PERC, cloud scaling, and signoff automation for advanced custom IC and SoC teams.
  20. Design for Manufacturability in EDALearn design for manufacturability in EDA: density checks, pattern matching, dummy fill, and automation methods that reduce silicon risk before tapeout.
  21. Calibre SVRF TVF Rule Decks GuideGuide to Siemens Calibre SVRF and TVF rule decks for physical verification: rule syntax, DRC/LVS deck structure, PERC checks, and debug best practices.
  22. DRC/LVS Verification Best PracticesMaster DRC and LVS physical verification. Learn best approaches for error resolution, rule deck optimization, and repeatable workflows.

Signoff and timing17 notes

  1. Timing Signoff Convergence in MCMMMaster the complexities of Multi-Corner Multi-Mode (MCMM) timing signoff to ensure silicon reliability and performance across all operating conditions.
  2. On-Chip Variation in Static TimingHow on-chip variation is modeled in static timing analysis, why derating guards against local delay spread, and what disciplined OCV signoff requires.
  3. Formal Equivalence in ASIC SignoffHow formal equivalence checking anchors ASIC signoff, from comparison points and clock gating to debugging non-equivalent results across every design stage.
  4. Timing Exceptions Without Signoff GapsA working discipline for false paths, multicycle paths, and min-max delay overrides so timing exceptions stay auditable from capture through STA signoff.
  5. ASIC Signoff Checks Before TapeoutA disciplined ASIC signoff checklist covering static timing, physical verification, power and IR drop, reliability, and functional evidence before tapeout.
  6. ASIC Signoff Evidence That ScalesBuild an ASIC signoff evidence flow that keeps checks, waivers, ownership, and handoff decisions traceable from final verification through tapeout.
  7. Multi-Corner Multi-Mode Timing AnalysisMaster the complexities of Multi-Corner Multi-Mode (MCMM) timing analysis to ensure silicon robustness across diverse PVT corners and operating modes.
  8. Static Timing Constraint ReviewA practical static timing constraint review workflow for checking clocks, exceptions, coverage, and handoff evidence before signoff.
  9. ASIC Signoff Checklist and HandoffA practical ASIC signoff checklist covering evidence, corner consistency, waivers, ownership, and the final handoff to manufacturing.
  10. Cadence Tempus Timing SignoffLearn how Cadence Tempus timing signoff automation improves MCMM STA, ECO closure, constraint checks, and reliable ASIC tape-out readiness.
  11. Synopsys PrimeTime Timing GuideLearn how Synopsys PrimeTime timing analysis supports STA signoff, SDC constraints, MCMM closure, ECO loops, and ASIC tape-out readiness.
  12. Tape-Out Support ServicesTape-out support services guide for ASIC and custom IC teams, covering signoff checks, release packages, foundry handoff, and risk reduction.
  13. Constraint-Driven SDC DesignLearn how constraint-driven SDC design improves timing closure, CDC checks, and signoff automation across ASIC and custom IC flows.
  14. Formal Verification in EDAExplore formal verification in EDA — JasperGold, VC Formal, and property checking. Learn how formal methods catch RTL bugs and accelerate signoff.
  15. Power Integrity and EMIR AnalysisPower integrity analysis for semiconductor designs: IR drop, electromigration, EMIR tools like RedHawk and Voltus, and reliable PDN techniques.
  16. Low Power Design and UPF AutomationMaster low power design with UPF (IEEE 1801). Learn power domains, isolation, level shifters, retention strategies, and multi-voltage EDA verification.
  17. Timing Closure Automation GuideLearn timing closure automation for semiconductor design using STA, signoff analysis, MCMM constraints, and optimization techniques for advanced process nodes.

Custom IC and layout15 notes

  1. Schematic-Driven Layout DisciplineHow schematic-driven layout keeps custom IC work connected, constrained, and verifiable, with practical automation hooks and team discipline that scales.
  2. Matching-Aware Analog FloorplanningHow constraint-driven flows make analog layout automation repeatable, from symmetry and matching rules to parasitic-aware routing and signoff evidence.
  3. Custom IC Design Automation PlaybookA practical playbook for automating custom IC design flows: scripting tools, guarding accuracy, and building team-wide reliability into every run.
  4. Analog Layout Automation EssentialsA practical guide to analog layout automation: PCells, constraint-driven placement, routing by net class, and verification hooks for consistent custom IC work.
  5. Scaling Custom IC Automation FrameworksLearn how to scale custom IC design automation frameworks to handle complex analog and mixed-signal layouts while maintaining tapeout reliability.
  6. Constraint-Driven Analog Layout ReviewA practical workflow for encoding analog layout constraints, reviewing generated geometry, and preserving designer intent through verification.
  7. Custom IC Automation for Safer TapeoutA practical guide for design teams that want dependable custom IC automation, from constraints and reusable scripts to review gates and readiness checklists.
  8. Virtuoso Schematic AutomationAutomate Cadence Virtuoso schematic entry, CDF checks, netlisting, and simulation setup with SKILL-driven custom IC design workflows.
  9. PCell and PCellXL DevelopmentLearn how Cadence PCell and PCellXL development automates parameterized layout, callbacks, CDF data, and verification-ready custom IC cells.
  10. IC Layout Automation GuideLearn how IC layout automation improves custom chip layout with SKILL, Tcl, Python, PCells, rule checks, and repeatable physical design flows.
  11. Custom IC Design AutomationCustom IC design automation guide for analog and mixed-signal teams using SKILL, Python, PDK data, verification, and reusable flows.
  12. Best Analog Layout Tasks to AutomateDiscover the best analog layout tasks to automate with Cadence SKILL, PCells, schematic-driven placement, and simulation workflows for faster custom IC design.
  13. GDSII OASIS Layout AutomationGuide to generating and validating GDSII and OASIS layout files for modern semiconductor flows, including hierarchy, layers, and data checks.
  14. Synopsys Custom Compiler AutomationLearn how to automate Synopsys Custom Compiler with Tcl/Tk scripting for layout, schematic, and simulation workflows in custom IC design.
  15. Virtuoso Layout Automation with SKILLCadence Virtuoso layout automation with SKILL scripting: reduce manual layout effort, create reusable flows, and improve custom IC design productivity.

Scripting and automation15 notes

  1. Tool-Agnostic Python Wrappers for EDALearn how to build robust Python wrappers that abstract EDA tool commands, ensuring portable scripts across different vendor toolchains and versions.
  2. EDA Scripting Library StructureA practical structure for EDA scripting libraries: module layout, stable interfaces, versioning, and review habits that keep automation maintainable at scale.
  3. Tcl Patterns for Chip Design TeamsPractical Tcl scripting patterns for chip design teams: structured flow control, safe defaults, layered logging, and reusable libraries across the toolflow.
  4. Automating EDA Tool Config with PythonLearn how to build robust, scalable Python wrappers for EDA tool configuration to eliminate manual setup errors and accelerate design cycle times.
  5. Defensive Python for EDA PipelinesBuild dependable Python automation for EDA pipelines with strict inputs, safe subprocess handling, clear evidence, and repeatable failure recovery.
  6. Perl Scripting for EDA CAD FlowsLearn how Perl scripting supports semiconductor CAD flows, log parsing, report automation, data cleanup, and legacy EDA infrastructure maintenance.
  7. Tcl Scripting for EDA AutomationLearn how Tcl scripting automates EDA setup, reports, regressions, and signoff checks across Cadence, Synopsys, and Siemens flows.
  8. VLSI Design Automation GuideVLSI design automation guide for ASIC teams, covering RTL, verification, synthesis, physical design, signoff, and reusable CAD flows.
  9. Chip Design Automation ServicesLearn how chip design automation services connect RTL, verification, layout, signoff, and CAD infrastructure for faster ASIC tape-outs.
  10. RTL Design Automation GuideLearn how RTL design automation accelerates ASIC and FPGA development with code generation, lint checks, formal verification, and timing-driven optimization.
  11. Python EDA Automation GuideComprehensive guide to Python for EDA automation — tool scripting, PCell development, PDK management, verification, and CAD infrastructure integration.
  12. DFT Design for Test AutomationLearn how design-for-test automation improves semiconductor test coverage, reduces time-to-market, and enables high-quality chip production at advanced nodes.
  13. Tcl/Tk for EDA Automation WorkflowsLearn Tcl/Tk EDA automation for simulation, layout, and verification workflows. Build reusable scripts that connect tools and reduce manual custom IC tasks.
  14. What Is EDA Automation?Understanding EDA automation: how scripting, tool integration, and workflow optimization accelerate semiconductor design cycles.
  15. Cadence SKILL Tutorial: Code ExamplesHands-on Cadence SKILL scripting tutorial with copy-paste code examples — syntax, PCells, CDF callbacks, and Virtuoso layout automation workflows.

CAD infrastructure and PDKs15 notes

  1. Design Data Management in Custom IC FlowsDesign data management for custom IC flows: library and cellview versioning, workspace discipline, release snapshots, and automation for reproducible signoff.
  2. Scalable CAD Tooling for Modern SoC DesignBuild robust, tool-agnostic CAD infrastructure for large-scale SoC projects by leveraging modular wrappers, resource scheduling, and reproducibility.
  3. Compute Farm Scheduling for EDAA practical guide to compute farm scheduling for EDA teams: workload classes, queue policy, license-aware dispatching, and the capacity signals that matter.
  4. PDK Version Discipline for TeamsWhy PDK version discipline matters for chip teams: pinning kits, managing corner and rule updates, qualifying upgrades, and keeping signoff reproducible.
  5. EDA Tool Environment VersioningVersioned EDA tool environments keep simulations, signoff, and tapeout evidence reproducible across teams, PDK updates, and long program lifecycles.
  6. Semiconductor CAD Infrastructure BlueprintBuild a dependable semiconductor CAD infrastructure with clear ownership, reproducible environments, scalable compute, and evidence-driven operations.
  7. CAD Compute Farm Scheduling for Chip TeamsA practical guide to scheduling EDA compute farm jobs, balancing license checkouts, queue priorities, and storage load across chip design teams.
  8. Remote EDA Environment GuideBuild secure remote EDA environments with Linux workstations, license servers, VPN access, VDI, storage, monitoring, and reproducible CAD flows.
  9. Secure Linux CAD OperationsSecure Linux CAD operations for EDA teams: harden workstations, protect licenses, isolate projects, and keep IC design flows productive.
  10. EDA Infrastructure EngineeringLearn how EDA infrastructure engineering keeps semiconductor design teams productive with Linux CAD operations, licensing, storage, and secure automation.
  11. Foundry PDK EnablementFoundry PDK enablement turns process data into validated techfiles, devices, rules, and automation so IC teams start design faster.
  12. Cloud EDA SaaS SolutionsCloud EDA SaaS guide for semiconductor teams: scalable tools, flexible licensing, secure deployment, and best practices for hybrid design flows.
  13. FlexNet Licensing for EDA ToolsComprehensive guide to FlexNet license management for EDA tools including setup, optimization, monitoring, and troubleshooting best practices.
  14. PDK Setup and Enablement GuideMaster foundry PDK setup for custom IC design: techfile config, validation scripts, deployment automation. Cut setup from weeks to days with proven methods.
  15. CAD Infrastructure for SemiconductorUnderstand CAD infrastructure for semiconductor teams: tool installs, license servers, PDK management, Linux environments, and secure access for IC design.

Mixed-signal verification10 notes

  1. Mixed-Signal Verification ArchitecturesExplore the design of robust mixed-signal verification environments, focusing on co-simulation efficiency, behavioral modeling, and regression strategies.
  2. Mixed-Signal Co-Simulation BasicsHow analog and digital simulators exchange data during co-simulation, what the handoff between solvers means, and how to structure mixed-signal testbenches.
  3. Mixed-Signal Regression TriageA practical triage workflow for mixed-signal regressions, covering baselines, noise separation, waveform-first debugging, and ownership rules that scale.
  4. Mixed-Signal Verification EvidenceBuild a practical evidence trail for mixed-signal verification by connecting analog measurements, digital checks, interfaces, regressions, and signoff reviews.
  5. Mixed-Signal Verification StrategiesExplore essential mixed-signal verification strategies for complex SoC designs, focusing on real-number modeling and co-simulation workflows.
  6. Mixed-Signal Verification PlanningPlan mixed-signal verification with clear interfaces, abstraction levels, checkers, coverage goals, and evidence for dependable signoff.
  7. Synopsys HSPICE SimulationLearn how Synopsys HSPICE simulation automation improves SPICE regression, corner sweeps, model validation, and analog signoff productivity.
  8. Synopsys StarRC ExtractionExplore Synopsys StarRC parasitic extraction flows for custom IC and ASIC signoff, including RC corners, SPEF output, EMIR handoff, and automation.
  9. Mixed-Signal Layout AutomationMixed-signal layout automation guide for analog-digital SoCs, covering isolation, matching, guard rings, routing, verification, and reuse.
  10. Mixed-Signal Verification GuideComprehensive guide to mixed-signal verification. Learn Verilog-AMS, real-number modeling, and co-simulation strategies for analog-digital SoC integration.

Industry and flows10 notes

  1. Semiconductor CAD Services GuideComprehensive guide to semiconductor CAD services: layout automation, physical verification, PDK setup, and infrastructure support for custom IC teams.
  2. Automotive Functional Safety ISO 26262Learn how ISO 26262 functional safety shapes automotive chip design. Covers ASIL levels, FMEDA, EDA tool qualification, and safety verification workflows.
  3. Chiplet Design and 3D IC ToolsChiplet-based design and 3D IC are transforming semiconductor workflows. Explore UCIe, heterogeneous integration, advanced packaging, and 3D IC EDA toolflows.
  4. AI EDA Tools GuideAI and ML are transforming EDA tools for chip design. Discover AI-driven layout, verification, and optimization in modern semiconductor workflows.
  5. India Semiconductor EcosystemIndia's semiconductor ecosystem is booming with ISM incentives and new fab projects. Explore EDA and design automation opportunities in this emerging VLSI hub.
  6. IP Porting and Migration GuideIP porting and migration services for semiconductor cross-technology node transfers. Covers schematic, layout, and validation workflows for IP reuse.
  7. Advanced Node VerificationMaster verification for advanced semiconductor nodes including FinFET and GAA at 7nm, 5nm, and 3nm. Covers DRC, LVS, reliability, and emerging challenges.
  8. RISC-V EDA Tools GuideComprehensive guide to RISC-V EDA tools including open-source and commercial flows for RISC-V core design, verification, and SoC integration.
  9. Open Source EDA Tools GuideComprehensive guide to open source EDA tools including OpenROAD, Yosys, and ngspice for modern semiconductor design and verification workflows.
  10. ASIC Flow and Platform Support GuideMaster the end-to-end ASIC design process, from RTL coding to physical verification, and understand modern platform enablement techniques.

Physical design9 notes

  1. Hierarchical SoC Floorplanning StrategiesMaster the art of hierarchical floorplanning to optimize area, timing, and routability in large-scale System-on-Chip (SoC) designs for advanced nodes.
  2. Clock Tree Synthesis Without Skew TrapsA practical guide to clock tree synthesis in physical design: skew targets, buffer planning, useful skew, and the signoff checks that keep clock timing stable.
  3. Physical Clock Mesh Hardening GuideA practical playbook for making clock distribution robust through layout planning, buffering strategy, and iterative signoff checks before tapeout.
  4. Consistent Tapeout Physical Design PlanA practical physical design playbook for stable floorplanning, routing, and handoff evidence with fixed ownership and reproducible signoff context.
  5. CDL, SPICE & Verilog Netlist FormatsLearn how Verilog, CDL, and SPICE netlists connect schematic capture, simulation, LVS, and tape-out flows for custom IC teams.
  6. Synopsys ICC2 PnR AutomationSynopsys ICC2 place and route automation guide covering floorplanning, CTS, routing, timing closure, ECOs, and scalable ASIC implementation flows.
  7. Cadence Innovus PnR GuideLearn Cadence Innovus PnR automation for floorplanning, placement, CTS, routing, timing closure, and signoff-ready digital implementation flows.
  8. Netlist Optimization GuideLearn netlist optimization for ASIC and custom IC flows, covering hierarchy cleanup, connectivity checks, timing, power, and signoff-ready automation.
  9. Physical Design EDA GuideLearn how physical design EDA connects floorplanning, placement, CTS, routing, timing closure, power integrity, and signoff for ASIC tape-out.