Antenna Checks in Physical Verification

What the Antenna Effect Actually Is

The antenna effect is a manufacturing-time reliability risk, not a subtlety of functional behavior. During plasma etch steps, exposed conductors collect charge from the plasma around them. A conductor connected to a transistor gate behaves like an antenna: it gathers charge in proportion to the conductor area exposed to the plasma, and that charge looks for a path through the gate.

When the path runs through the thin gate oxide, the oxide can be stressed or permanently damaged. The damage is not always obvious at wafer test. A slightly leaky gate, a shifted threshold, or a latent weakness that surfaces as early life failure can all trace back to charging events during fabrication. That is why the industry treats gate charging as a signoff item rather than a yield experiment: the check is cheap to run, and the alternative is discovering the problem after encapsulation.

Antenna checking verifies that every conductor attached to a gate stays within the charge collection limits defined by the process. The limits and the measurement mechanics live in the physical verification deck, and they are evaluated per net and per conductor layer, using the connectivity that the layout already implies.

Antenna Ratios: How the Rules Read

The core comparison is between the charge collecting area of a conductor and the area of the gate it reaches. The classic quantity is the antenna ratio: conductor area divided by gate area, computed for the portion of the net routed up to and including each layer. Modern decks often formalize two measurements: an area ratio based on the conductor top surface, and a perimeter or sidewall ratio that accounts for the vertical faces of a wire.

Every limit is foundry supplied and varies by layer, by device type, and by process option, so no number should ever be assumed. Cumulative behavior is the key subtlety. Charge collected on lower metals counts toward what the upper layers present to the gate, which means a violation is a property of the net's whole routing history, not of a single segment in isolation.

Reading the rule deck closely pays for itself: which layers participate, which devices are exempt, how the ratio is composed, and how multi-layer connections are handled. Teams that understand those switches can often explain a violation in minutes and fix it with one targeted change.

Where Antenna Checking Fits the Flow

Antenna checks need connectivity. The deck must know which conductors reach which gates, so the check typically runs as part of, or immediately after, LVS. It traces nets from gate to pad, measures what connects where, and reports violations against verified connectivity rather than geometry alone. Because upper metal routing continues late in the schedule, antenna results age quickly. A clean result early in the week can be stale by the end of it.

Productive teams run the check incrementally: block level while routing is still fluid, chip level once top level metal is complete, and always as part of the final signoff gate. Hierarchy deserves attention. A block verified in isolation can still produce chip level findings once its pins connect to long top level routes, because the connecting wire becomes part of the antenna seen from the gate. The run that counts for signoff is the one executed on the assembled database with the deck version that will accompany tapeout.

Diode Insertion: The Standard Fix

The most common remedy for an antenna violation is an antenna diode: a small reverse biased junction placed near the gate to give collected charge a safe discharge path. Instead of stress on the gate oxide, the charge flows through the diode to the substrate. Placement matters. Protection depends on the wire between the diode and the gate staying short, so the diode belongs as close to the gate as the layout allows.

Insertion is not free: every diode adds area, capacitance, and a junction that must satisfy its own layout rules. On sensitive analog nodes or high speed signals the added load may be unacceptable, and that trade is an engineering decision, not a checkbox. Modern flows often automate diode insertion during routing, letting the deck or a script place diodes on violating nets while the routing is still open.

Whatever the mechanism, the result must stay consistent with the rest of the flow: a physical only diode that never appears in the schematic, the netlist, or the extraction is a classic late stage surprise. Record which nets received diodes and propagate that change through LVS and parasitic extraction deliberately.

Jumpers, Segments, and Metal Fixes

Not every violation needs a diode, and some nets cannot take one. The alternative is to break the antenna itself: reroute part of the connection on another layer so the charge collecting length attached to the gate is split into smaller segments, or move the run to a layer where the process provides more headroom. Because charge accumulation is cumulative along the path, a well placed layer change can bring a net under its limit without touching circuit function.

These fixes trade routing resources and vias. Each added via and segment carries its own implications for resistance, electromigration, and timing, so jumper fixes belong in the normal engineering change process rather than a last minute scramble. The trade is usually easiest early, while routing is still open and an automated pass can apply the change at scale. In practice most teams use both families of fix, choosing per net: diodes where protection is cheap, reroutes where the net is sensitive, and a documented combination when neither alone is enough.

Debugging Antenna Violations Methodically

Debug starts from the report. Each violation names a net, the gate involved, and the ratio numbers that exceeded the limits, layer by layer. The first question is always where the charge accumulates fastest: read the per layer numbers from bottom to top and the growth pattern tells the story. From there, trace the net in the layout, confirm the connectivity matches what the deck believed, and decide whether the finding is real.

Common artifacts include incompletely connected routing, stale or missing labels, a deck option that does not match the process module being built, and fill or dummy shapes that should have been excluded. A phantom violation is usually faster to eliminate by fixing the database or the deck option than by adding hardware. Real violations get a fix, and every fix is re-verified with an incremental run before it is folded into the main database.

Keep a short log of net, cause, and fix. Most designs have only a handful of root causes behind all of their antenna findings, and the log turns the tenth violation into a five minute job.

Discipline, Waivers, and Signoff Evidence

Discipline is what keeps antenna checking cheap: run it on schedule, on the right database, with the matched deck version, and fix findings while routing is still easy to change. The expensive version of antenna debug is the one that starts the night before tapeout. Waivers exist for genuine exceptions, such as a net whose risk is mitigated another way or a rule that does not apply to the selected process option.

But a waiver is engineering evidence, not silence: it records the net, the technical rationale, the approver, and the date, and it is revisited whenever the routing changes. An unexplained exception is an audit finding waiting to happen. The final antenna report joins the tapeout evidence package alongside DRC and LVS results, tied to the exact database revision that was signed off.

That traceability is the point. When someone asks later how gate charging risk was controlled, the answer is a report, a revision number, and a record of every deliberate exception.