SkyCadEda · Bengaluru, India

CAD/EDA engineering for custom IC teams: SKILL automation, PDKs and DRC/LVS runsets.

We bring up Virtuoso and its licensing, install and QA foundry PDKs, write Calibre, PVS and Pegasus runsets, automate layout work in SKILL and Tcl, and run the RHEL/AlmaLinux CAD environment underneath. We are also Stabie-Soft's reseller in India for the SLAM layout and schematic tools.

Discuss your projectSee all services
years combined CAD/EDA experience
25+
engineering tracks
4
automation languages
SKILL · Tcl · Python
verification decks
Calibre · PVS · Pegasus · Assura
Layout of a CMOS inverter standard cellSkyWater SKY130 sky130_fd_sc_hd__inv_1, 1.38 by 2.72 micrometres: n-well, p and n diffusion, a polysilicon gate, local-interconnect and metal-1 power rails, with a 0.14 micrometre ruler and a metal-1 spacing DRC marker.AYVPWRVGND0.150m1.20.120<0.140pfet_01v8W=1.00L=0.15nfet_01v8W=0.65L=0.15
X 0.605 Y 1.165 µm
Fig. 1 sky130_fd_sc_hd__inv_1 · 1.38 × 2.72 µmnwelldiffpolyli1met1
Tools & formats
  • Cadence Virtuoso
  • SKILL
  • Tcl/Tk
  • Python
  • Calibre
  • Pegasus
  • PVS
  • Assura
  • OpenAccess
  • GDSII
Who we work with
  • Foundry
  • IDM
  • Fabless
  • IP providers
  • Design houses

Why teams call us

Four kinds of CAD work we take off a design team

Most engagements start with one of these. The output is code, decks and documented setups your team keeps running after we hand over.

  • Repetitive layout and reporting work

    SKILL and Tcl scripts for recurring layout, schematic, reporting and utility tasks, so designers spend their time on design decisions.

  • PDK and flow setup

    Techfiles, CDF callbacks, device models and layer maps, installed and checked when a new kit or a foundry update lands.

  • DRC/LVS runsets

    Rule decks for Calibre (SVRF/TVF), Pegasus, PVS and Assura, plus waiver management and automated DRC/LVS flows.

  • CAD operations

    Tool installs, FlexNet licensing, Grid Engine queues and remote access on RHEL/AlmaLinux for distributed teams.

flag_met1_width.ilVirtuoso CIW
; flag met1 shapes narrower than 0.14um, drop a marker
cv = dbOpenCellViewByType("demo_lib" "inv_1" "layout"
                          "maskLayout" "a")
count = 0
foreach(shape cv~>shapes
  when(shape~>layerName == "met1"
       && shape~>objType == "rect"
    let((bb w)
      bb = shape~>bBox
      w  = min(xCoord(cadr(bb)) - xCoord(car(bb))
               yCoord(cadr(bb)) - yCoord(car(bb)))
      when(w < 0.14
        dbCreateRect(cv list("marker" "error") bb)
        count++))))
printf("met1 width violations: %d\n" count)
dbSave(cv)
met1 width violations: 0
t
Fig. 2 A SKILL width check of the kind we write for layout teams

A good fit when

  • Manual layout or verification tasks are slowing project milestones.
  • A new PDK, node migration, or foundry update needs reliable enablement support.
  • Internal CAD teams need extra bandwidth for automation and rollout work.
  • Distributed engineers need secure, operationally clean access to EDA environments.
Discuss your projectSee how we staff work

Services

What we build and run

Eight service lines, from SKILL layout automation to secure remote access for design teams. Each one has its own page.

Stabie-Soft SLAM for layout, schematic, and DRC/LVS

We are Stabie-Soft's official resale partner in India. We help teams evaluate SLAM on their own designs, deploy it on Linux, and automate work through its built-in Tcl API.

View SLAM products
Slam-Edit
Layout editing for large custom-IC databases with Linux-native deployment and automation hooks.
Slam-View
Fast review for layout and mask data without pulling in a full editor workflow.
Scheture & Secours
Schematic capture, Verilog/CDL/SPICE translation, and schematic-driven layout.
Verification
In-tool DRC/LVS, compare utilities, and floorplanning support for fast debug loops.
printCellInfo.tclSLAM Tcl API
# print every object in a cell, grouped by type
proc printCellInfo { cellId } {
    foreach type { rectangle polygon path
                   instance pin via text } {
        edbSeq loopVar $cellId $type {
            puts [edbFetchObject $cellId $loopVar]
        }
    }
}
Fig. 3 SLAM exposes its layout database to Tcl: edbSeq walks objects, edbFetchObject reads them

Engagement model

Start with the current setup. End with a documented, working rollout.

We work in three steps: map what you already have, plan the rollout, then deploy, document and support it.

  1. Step 1

    Understand the current setup

    We start by mapping the systems you already have, the target flow, the user model, and the security boundaries.

  2. Step 2

    Lay out the rollout plan

    We turn that into an implementation plan, deployment sequence, and working documentation while the environment is being built.

  3. Step 3

    Deploy, document, support

    We finish the setup, validate it with the team, hand over clear notes, and stay available after go-live.

Support can continue after go-live for fixes, tuning, and day-to-day CAD/EDA ownership. Discuss your project

Common engagements

Work we are usually asked to do

What comes in, what we hand back, and the tools involved. Each links to the service page with the detail.

  • Virtuoso Studio IC25 bring-up on RHEL/AlmaLinux

    Input
    A new or upgraded Virtuoso installation on shared Linux servers.
    Deliverable
    A user-ready environment, with cdsmgr/FlexNet licensing set up to coexist with the rest of your EDA licenses.
    Tools
    Virtuoso IC25 · cdsmgr · FlexNet · RHEL/AlmaLinux

  • PDK install and QA for foundry kits

    Input
    A kit drop or foundry update: tsmc18rf, tsmcN22, gf12nm and similar.
    Deliverable
    An installed, validated PDK: techfile, layer maps, CDF parameters and callbacks, device models.
    Tools
    Virtuoso · Techfile · CDF · BSIM/PSP

  • DRC/LVS runset development and waiver flow

    Input
    Foundry design rules, or existing decks that need rework.
    Deliverable
    Rule decks with runset QA, waiver management and automated DRC/LVS flows.
    Tools
    Calibre SVRF/TVF · Pegasus · PVS · Assura

  • SKILL and PCell automation for layout teams

    Input
    Layout tasks done by hand, or devices drawn the same way every time.
    Deliverable
    SKILL utilities and DRC-aware SKILL or PyCell PCells with CDF callbacks.
    Tools
    SKILL · PyCell · Virtuoso

  • Grid Engine farm and ClioSoft SOS data management

    Input
    Shared compute and design data across a team.
    Deliverable
    Sun Grid Engine workload distribution, ClioSoft SOS installation, repository setup and license server handling.
    Tools
    Sun Grid Engine · ClioSoft SOS · FlexNet

FAQ

Questions teams ask before they reach out

Not covered here? Email [email protected].

What kinds of EDA work can SkyCadEda automate?
We support layout automation, schematic and simulation utilities, PDK setup, physical verification flows, PCell development, IP migration, and CAD infrastructure scripting.
Can you work with our existing CAD methodology and internal tools?
Yes. We usually integrate into the Cadence, Synopsys, Calibre, Pegasus, Assura, and Linux environments teams already use instead of forcing a parallel flow.
How do you handle secure collaboration on sensitive design IP?
We support secure remote-access and CAD infrastructure patterns that keep design data inside controlled environments while still enabling distributed engineering teams to execute.
Do you deliver standalone scripts or full integration support?
Both. Engagements can range from targeted utilities to broader implementation, validation, rollout, and handoff support across design, CAD, and verification teams.

Discuss your project

A short description of the flow and the problem is enough to start. Replies come from [email protected].

Office
Bengaluru, IN
Time zone
IST (UTC+05:30)

Tools, node or PDK, and what is blocking you. At least 20 characters.

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