Metal Fill and Density Signoff Discipline

Why Density Rules Exist

Modern manufacturing processes depend on the wafer being exposed, etched, and polished in a broadly uniform way. If one region of a die contains long stretches of bare substrate while another region is dense with metal, each step of lithography, etch, and chemical mechanical polishing behaves differently in those places. Density rules exist to keep layer coverage inside a window the process was qualified for.

Foundries express them as a minimum and sometimes a maximum percentage of a given layer that must be present inside a square window of fixed size, often with a step that slides the window across the whole die. The check is purely geometric: it counts drawn area, not function. That is why a layout can pass every connectivity and timing check and still fail density, and why fill insertion is a standard stage between routing and tapeout rather than an optional cleanup step.

How Density Windows Are Specified

A typical foundry rule deck defines, per layer, a window size such as a few dozen microns on a side, a coverage range, and the distance the window advances between evaluations. Some decks add rules for multi-window regions, notch exceptions, or special zones near macro boundaries. The rules differ by layer: contact and via layers usually have lower minimums than metal layers, and top metals often carry their own values because of how planarization behaves at the upper levels.

What matters for a design team is that these numbers are versioned with the process design kit. Running density against an old deck silently checks the wrong window, and a wafer lot processed under a newer rule set can fail even though the signoff report was clean. Treat the density section of the deck like any other signoff input: pinned, reviewed, and updated together with the PDK.

The Fill Insertion Flow

Fill insertion is the step that adds dummy geometry to bring every window inside its required range. The flow reads the routed database, the layer stack, and the fill rules, computes coverage per window, and then places floating or grounded fill shapes where coverage is short. Good fill engines respect a set of constraints that matter as much as the density numbers themselves: fill must keep spacing to active nets, must not create new design rule violations, must honor keepouts around sensitive analog structures, and in advanced nodes must follow rules about which fill shapes may connect to which wells or power structures.

After insertion the flow rechecks density and reruns DRC on the filled database, because fill that fixes a coverage number while introducing a spacing violation has only moved the problem. The output of this stage is the database that goes to signoff, so its provenance should be recorded.

Verification and Signoff

Density signoff should always run on the final database, after fill and after any engineering change orders. A common mistake is verifying density on a pre-fill snapshot and assuming the fill tool guarantees the rest. The signoff run uses the same deck and window definitions the foundry will apply, and its report lists each failing window with location and layer.

Review that report rather than a summary count: a handful of marginal windows near a macro may be acceptable with documented waivers, while a systematic shortage on one layer points to a floorplan or fill-configuration problem that a waiver cannot fix. On the schedule side, leave real time for this stage. Density verification and fill repair on a large die can iterate several times, especially after late changes, and compressing it into the final weekend is how density escapes reach the foundry.

Fill Interactions With Timing and Reliability

Fill is not electrically invisible. Floating fill couples capacitively to nearby routed nets, so insertion can shift parasitic values that extraction and static timing depend on. The discipline that keeps this manageable is ordering: route, insert fill, extract the filled database, then time it. If timing fixes arrive after fill, decide explicitly whether they invalidate the fill run, and rerun extraction on whatever database is actually final.

Grounded fill changes the picture again, since attached fill can act as shielding or add loading deliberately, and the extraction setup must know which shapes are grounded and to which net. Teams that skip the re-extraction step sometimes see silicon timing differ from signoff timing by exactly the amount the fill added, which is a preventable and embarrassing discrepancy in any post-silicon review.

Analog and Mixed-Signal Considerations

Analog blocks deserve stricter fill handling than digital regions. Matching structures such as differential pairs, current mirrors, and resistor or capacitor arrays rely on surroundings being symmetric; a fill algorithm that dumps asymmetric dummy shapes next to one device and not its pair can degrade matching that careful layout work created. Practical mitigations include marking sensitive regions with fill blockages or keepouts, running fill in a mode that preserves symmetry where the tool supports it, and reviewing fill inside analog blocks by hand rather than trusting the report alone.

Mixed-signal boundaries need attention too: fill placed near a noisy digital boundary differs in purpose from fill near a quiet analog core, and blanket fill settings across both can be counterproductive. The extra review time is small compared with the debugging cost of a matching failure found at silicon.

Common Failure Modes and Practical Habits

Several failure modes recur across teams. Density checked against a stale deck produces clean reports for the wrong process. Fill run before the final route leaves coverage gaps that nobody rechecks. Fill inserted without spacing awareness passes density and fails DRC. Waivers are granted for failing windows without recording why, so the next revision re-litigates them from scratch. The habits that prevent these are simple: pin the deck version with the signoff result, run density as part of every milestone rather than only at the end, always regenerate and reverify fill after any post-fill change, and keep waiver records attached to the failing window coordinates.

None of this requires new tooling. It requires treating density and fill as first-class signoff steps with the same versioning discipline as timing or LVS, which is what the foundry already assumes when it accepts your tapeout.