Low Power Design and UPF Automation

Why Low Power Design Matters

Power consumption has become the primary constraint in modern semiconductor design. From mobile SoCs running on battery to data center processors consuming kilowatts, managing power is no longer optional. Leakage current at advanced nodes below 7nm can account for 30 to 40 percent of total power, and dynamic power density creates thermal hotspots that limit performance.

Low power design addresses these challenges through a combination of architectural decisions, circuit techniques, and EDA-driven automation. The Unified Power Format (UPF), standardized as IEEE 1801, provides the language bridge that carries power intent from specification through implementation to verification. Without a formal power intent specification, each design stage must independently interpret power requirements, leading to inconsistencies, silicon bugs, and costly respins.

For custom IC teams working with Cadence Virtuoso, Synopsys Custom Compiler, or mixed-signal flows, low power design adds another dimension of complexity. Analog blocks may operate at different voltages than digital controllers, isolation strategies must preserve signal integrity, and verification must cover all power state transitions. SkyCadEda's EDA automation services help teams integrate low power methodologies into their existing flows without disrupting established design practices.

The UPF Standard: IEEE 1801

The Unified Power Format was first released in 2007 as a Si2 standard and adopted by IEEE as IEEE 1801 in 2009. The standard has evolved through three major versions: UPF 1.0 (IEEE 1801-2009), UPF 2.0 (IEEE 1801-2013), and UPF 3.0 (IEEE 1801-2015). Each version expanded capabilities to handle increasingly complex power architectures.

UPF 1.0 established the foundation with power domains, isolation cells, level shifters, and power switches. UPF 2.0 added support for supply sets, power state tables, and enhanced modeling of supply networks. UPF 3.0 unified the UPF and CPF ecosystems, introduced supply set handling refinements, and improved support for hierarchical design methodologies where subsystems carry their own power intent.

The key concept in UPF is the power domain: a logical grouping of design elements that share a common power supply. Each domain has supply ports, power states, and associated strategies for handling interactions with other domains at different voltage levels or power states. The UPF file specifies these domains and their behaviors, while EDA tools interpret the UPF to insert physical cells, generate power-aware netlists, and verify correctness.

Power Domains and Supply Sets

A power domain in UPF groups design elements that share a common power supply rail. The top-level domain, typically called the design domain, represents the always-on supply. Subordinate domains can be independently powered down, voltage-scaled, or placed in retention mode. Each domain has primary supply nets for VDD and VSS, and may have additional supplies for SRAM arrays, I/O rings, or always-on logic.

Supply sets, introduced in UPF 2.0, bundle related supply nets into a named collection. For example, a supply set called VDD_LOW might contain the primary power net, ground net, and any bias nets. This abstraction simplifies UPF scripts and makes power intent more readable. When a power domain references a supply set, it inherits all the bundled supplies automatically.

Power state tables define the legal operating states for each supply or supply set. A typical table specifies that a supply can be in ON, OFF, or partial states (such as retention voltage). These tables serve as the contract between the designer's intent and the EDA tools that implement and verify the design. Tools check that the physical implementation can support all declared power states and flag violations during verification.

Isolation, Level Shifters, and Retention

When signals cross from one power domain to another, three types of specialized cells may be required. Isolation cells clamp signals to known values when the source domain is powered off, preventing floating inputs from causing leakage or metastability in the receiving domain. Common isolation strategies include clamping to zero, clamping to one, or clamping to the last driven value.

Level shifters translate signal voltage levels between domains operating at different voltages. A signal crossing from a 0.7V domain to a 0.9V domain requires a low-to-high level shifter to ensure the receiving domain sees valid logic levels. Similarly, high-to-low level shifters prevent overvoltage stress on transistors in the lower-voltage domain. Without proper level shifting, signals may not meet threshold voltages, causing functional failures or increased leakage.

Retention registers preserve their state when their power domain is shut down. A retention register contains a balloon latch that holds the saved value at a lower retention voltage while the main register loses power. When the domain powers back on, the retention register restores its saved value before normal operation resumes. UPF specifies which registers need retention and the save-restore behavior through the set_retention command and associated control signals.

Power Gating and Switch Architecture

Power gating uses header switches (PMOS transistors in the VDD path) or footer switches (NMOS transistors in the VSS path) to cut off the supply to a power domain. The switch network must handle the inrush current when the domain powers on, which can be several times the steady-state current. Rush-through current management requires staged power-on sequences with gradually enabled switch chains.

UPF models power switches with the create_power_switch command, specifying the input supply, output supply, control signals, and on/off states. The command defines the switch as a logical abstraction; the physical implementation chooses the actual transistor-level topology based on the foundry library and design constraints. EDA tools insert the physical switches during implementation and verify that the switch network meets IR drop and electromigration requirements.

Power state tables work in conjunction with switches to define valid sequences. For example, a domain may require its isolation to be enabled before its power switch opens, and the retention save to complete before the supply drops below the retention threshold. These sequencing constraints are specified in UPF and enforced during verification to prevent data corruption during power transitions.

UPF in the EDA Tool Flow

UPF integrates into every stage of the digital implementation flow. During RTL design, the UPF file is created alongside the HDL code to capture power intent. At synthesis, tools like Synopsys Design Compiler or Cadence Genus read the UPF to insert isolation cells and level shifters into the gate-level netlist. During place-and-route with Synopsys IC Compiler II or Cadence Innovus, the UPF guides physical placement of power switches, retention registers, and always-on buffers.

Static timing analysis with Synopsys PrimeTime or Cadence Tempus uses UPF to perform multi-mode multi-corner (MMMC) analysis across different power states. Each power state may have different supply voltages, which affect cell delays and interconnect timing. The timing signoff must be clean across all legal power states, not just the nominal operating condition.

For physical verification, Siemens Calibre and Cadence PVS read the UPF to check that isolation cells are correctly placed at domain boundaries, level shifters are present where required, and the power switch network is properly connected. The physical verification tool compares the layout against the UPF intent and reports any mismatches as errors that must be corrected before tapeout.

Low Power Verification Strategies

Low power verification requires a fundamentally different approach from traditional functional verification. The design must be verified not only for functional correctness but also for correct behavior during power state transitions. UPF-aware simulation tools, such as Synopsys VCS with UPF or Cadence Xcelium with power-aware mode, inject power supply behavior into the simulation to model domain shutdown, isolation clamping, and retention save-restore sequences.

Formal verification with UPF, using tools like Synopsys VC Formal or Cadence JasperGold, can exhaustively verify power sequencing properties. For example, a formal property might state that isolation is always active before the source domain powers off, or that retention save completes before the supply drops below the retention threshold. Formal methods catch corner-case violations that simulation may miss due to incomplete stimulus coverage.

Power-aware linting and CDC (clock domain crossing) analysis must also account for UPF. A signal crossing a power domain boundary may need different treatment than a signal crossing only a clock domain boundary. Tools like Synopsys Spyglass and Cadence Conformal integrate UPF awareness into their analysis engines to catch these mixed-domain issues early in the design flow.

Low Power Design for Custom and Mixed-Signal ICs

Custom and mixed-signal designs present unique low power challenges. Analog blocks, such as PLLs, ADCs, and voltage regulators, often have strict supply requirements that conflict with digital power management strategies. An analog block may require a clean, always-on supply while the surrounding digital logic uses aggressive power gating. UPF addresses this through the create_power_domain command with the -elements option to precisely specify which cells belong to each domain.

In Cadence Virtuoso flows, low power intent is captured in the schematic and propagated to the layout. PCell libraries for isolation cells, level shifters, and retention registers must be available in the Virtuoso technology library. SKILL scripts can automate the insertion and verification of these cells in the custom design environment, reducing manual effort and ensuring consistency with the digital flow's UPF specification.

For teams using mixed-signal verification, the analog and digital domains must be co-simulated with accurate power models. Real-number modeling (RNM) techniques represent analog behavior as discrete values that are compatible with digital simulation, enabling fast mixed-signal verification of power management circuits. The UPF specification anchors the power intent across both domains, ensuring that the verification environment accurately reflects the silicon's power architecture.

UPF Automation Best Practices

Effective UPF adoption requires disciplined methodology and automation. Start by defining the power architecture early in the design cycle, before RTL is complete. The power architect should create a power state table that enumerates all legal power states and transitions. This table becomes the specification that all downstream tools and verification environments reference.

Use hierarchical UPF to modularize power intent for large SoCs. Each subsystem team maintains its own UPF file that describes the subsystem's internal power domains and strategies. The top-level integration UPF references these subsystem UPFs and adds the inter-domain strategies. This approach scales to designs with hundreds of power domains and prevents the top-level UPF from becoming unmanageable.

Automate UPF quality checks with TCL scripts that verify naming conventions, check for missing isolation at domain boundaries, and validate power state table completeness. Tools like Synopsys VC LP provide comprehensive low power checks that catch common UPF errors before they propagate to implementation. Integrating these checks into the CI/CD pipeline ensures that UPF violations are caught within hours of introduction, not weeks later during signoff.

Conclusion and Next Steps

Low power design with UPF is no longer optional for modern semiconductor projects. The combination of advanced node leakage, thermal constraints, and market demands for energy-efficient products makes formalized power intent a baseline requirement. UPF provides the standard language that enables consistent power specification across all EDA tools and design stages.

For teams adopting low power methodologies, the investment in UPF infrastructure pays dividends across every project. The power intent specification becomes a reusable asset that captures institutional knowledge about power management decisions. Automated verification flows catch power-related bugs early, reducing the risk of silicon respins that cost millions of dollars and months of schedule delay.

SkyCadEda helps semiconductor teams integrate low power design methodologies into their existing EDA flows. From UPF script development and tool automation to power-aware verification and signoff, our services cover the full spectrum of low power design challenges. Contact us to discuss how we can accelerate your low power design adoption.

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